How a Solar Inverter Makes AC: H-Bridges, PWM, Harmonics and Grid Synchronisation

A solar string gives you direct current at a few hundred volts. Your fans, pumps and the DISCOM line expect a 50 Hz sine wave at 230 V, or 415 V between phases. The inverter closes that gap with switches that turn on and off thousands of times a second, and the mathematics turns those blunt pulses into a clean sine wave.

We build the idea from first principles, from the grid as a mathematical target to the H-bridge, sinusoidal pulse-width modulation (PWM), harmonics, the output filter, grid synchronisation and the DC-link capacitor. Every symbol is defined before use and every number was checked by calculation. For the DC side of the same machine, see how MPPT and DC-DC converters work.

Equipment values are illustrative typical datasheet figures, not any product's specification; use your own inverter's datasheet. PV strings are live whenever light falls on them, and work inside an inverter belongs to qualified, licensed electricians.

The grid as a target: voltage and power

First define the waveform we are aiming for. The symbols are:

• $v(t)$: instantaneous voltage (V); $\hat V$: its peak (V)
• $f$: grid frequency (Hz), 50 Hz in India; $T = 1/f$: period (s)
• $\omega = 2\pi f$: angular frequency (rad/s); $\varphi$: phase angle (rad)
• $V_{\mathrm{rms}}$: root-mean-square (effective) voltage (V)

The grid voltage is a sinusoid:

At 50 Hz, $\omega = 314.16\,\mathrm{rad/s}$. The rms value is the steady DC voltage that heats a resistor equally, found from the mean of $v^2$ over one period:

Set $\varphi = 0$ and use $\sin^2 x = \tfrac12(1-\cos 2x)$:

The cosine completes two whole cycles per period, so its average is zero and only the constant half survives:

For 230 V, $\hat V = \sqrt2 \times 230\,\mathrm{V} = 325.3\,\mathrm{V}$. That peak, not 230 V, is what the inverter must be able to create.

Three phases and the factor of root three

A three-phase supply has three sinusoids displaced by 120 degrees. With $V_{\mathrm{ph}}$ the rms phase-to-neutral voltage, take phase a as reference and phase b lagging by 120 degrees. The line-to-line voltage is the phasor difference:

Here $e^{-j120^\circ} = -\tfrac12 - j\tfrac{\sqrt3}{2}$. Pythagoras gives the magnitude:

The line voltage is $\sqrt3$ times the phase voltage and leads phase a by 30 degrees. A 415 V line corresponds to a phase voltage of 239.6 V. The harmonised nominal is 230/400 V; the arithmetic is the same, so check which value your DISCOM declares.

Why single-phase power pulses and three-phase power does not

Let the inverter push current $i = \hat I\sin\omega t$ in phase with the voltage (unity power factor). Instantaneous power is their product:

Since $P = V_{\mathrm{rms}}I_{\mathrm{rms}}$ is the average power, this is:

Power swings between 0 and $2P$ at 100 Hz. A 5 kW inverter on 230 V carries 21.7 A rms (30.7 A peak), yet its power goes from 0 to 10 kW a hundred times a second. The array supplies nearly constant power, so the DC-link capacitor absorbs the difference; we size it later.

For three balanced phases, with $\theta = \omega t$, the power is the sum of three such terms:

Apply $\sin^2x = \tfrac12(1-\cos2x)$ to each. The three cosines are 120 degrees apart, so they sum to zero:

Balanced three-phase power is constant, with no 100 Hz ripple, so a three-phase inverter needs far less DC-link capacitance than a single-phase one.

The H-bridge: building AC from four switches

A single-phase bridge has four switches (IGBTs or MOSFETs, each with a diode across it) in two legs between the DC-link rails. Let $V_{dc}$ be the DC-link voltage. Leg A has S1 above S2, and leg B has S3 above S4. The filter and grid sit between the two mid-points. Each mid-point, measured from the negative rail, is either 0 or $V_{dc}$:

Shoot-through and dead-time

If both switches of a leg conduct, only the loop inductance $L_{\mathrm{loop}}$ (H) and device resistance limit the current:

For an assumed 50 nH loop, that is 8 kA per microsecond, and the device fails within microseconds unless protection acts. Because switches turn off more slowly than they turn on, gate drivers insert a dead-time $t_d$ when both are off, and the load current flows through a diode.

Dead-time costs voltage. With $f_s$ the switching frequency, each leg's average output falls by about:

For $V_{dc} = 400\,\mathrm{V}$, $t_d = 1\,\mu\mathrm{s}$ and $f_s = 16\,\mathrm{kHz}$, this is 6.4 V per leg and up to 12.8 V across the bridge, 3.9% of the 325 V peak. Its sign follows the current direction, so firmware compensates for it.

Sinusoidal PWM and the volt-second argument

Switching between +V_dc and −V_dc is not yet a sine wave. Sinusoidal PWM (SPWM) compares a slow reference with a fast carrier. The symbols are:

• $v_{\mathrm{ref}}$: sinusoidal reference at grid frequency (V); $v_{\mathrm{tri}}$: triangular carrier of peak $\hat V_{\mathrm{tri}}$ at frequency $f_s$
• $m_a = \hat V_{\mathrm{ref}}/\hat V_{\mathrm{tri}}$: amplitude modulation index; $m_f = f_s/f$: frequency ratio (both dimensionless)
• $d$: duty ratio, the fraction of a carrier period $T_s = 1/f_s$ that S1 and S4 are on

In bipolar switching, S1 and S4 are on when $v_{\mathrm{ref}} \gt v_{\mathrm{tri}}$, and S2 and S3 otherwise. Assume $f_s \gg f$, so the reference barely moves in one carrier period. The triangle ramps linearly from $-\hat V_{\mathrm{tri}}$ to $+\hat V_{\mathrm{tri}}$ and sits below the reference for the fraction:

The bridge gives +V_dc for a fraction $d$ and −V_dc for the rest. Volt-seconds per period divided by $T_s$ is the local average:

Substituting $v_{\mathrm{ref}} = m_a\hat V_{\mathrm{tri}}\sin\omega t$:

The filter inductor responds to the integral of voltage, so after filtering what remains is this local average, a sine of peak $m_aV_{dc}$. It holds in the linear region $m_a \le 1$. Beyond 1, low-order harmonics appear; the extreme is a square wave with fundamental $4V_{dc}/\pi = 1.273\,V_{dc}$.

Worked example. A 230 V grid peaks at 325.3 V. On a 400 V link, $m_a = 325.3/400 = 0.813$. At the 253 V upper case, $357.8/400 = 0.894$, still linear, which is a sensible 10% headroom.

Bipolar versus unipolar, and where the harmonics land

In unipolar switching, leg A follows $+v_{\mathrm{ref}}$ and leg B follows $-v_{\mathrm{ref}}$. The average is the same, $m_aV_{dc}\sin\omega t$, but the output steps between +V_dc, 0 and −V_dc in steps of V_dc and not 2V_dc, and the filter sees pulses at twice the carrier frequency.

These positions are the standard textbook result for a synchronised carrier with integer $m_f$. Real inverters often free-run the carrier, so sidebands shift slightly, but the clusters stay near $f_s$ or $2f_s$. For $m_a \le 1$ there are no significant harmonics below the carrier frequency. A numerical simulation at $m_a = 0.9$ and $V_{dc} = 400\,\mathrm{V}$ gave a fundamental of 359.8 V against 360 V predicted.

How high must the DC-link voltage be?

The output peak is at most $m_aV_{dc}$, so the linear region sets a floor:

At $m_a = 1$ and 230 V this is 325.3 V. Real designs add margin. Take a 10% high grid (253 V) and $m_a$ limited to 0.95:

Hence the common 380 to 400 V DC link. A string below that is lifted by a boost stage, covered in the MPPT and DC-DC converter guide.

Three-phase: deriving 0.612

In a three-phase bridge, each leg voltage relative to the DC mid-point swings between $\pm V_{dc}/2$. The same SPWM argument gives:

The line voltage is their difference. Using $\sin A - \sin B = 2\cos\tfrac{A+B}{2}\sin\tfrac{A-B}{2}$, the bracket becomes $\sqrt3\sin(\omega t + 30^\circ)$:

Dividing the peak by $\sqrt2$ gives the rms line voltage:

Plain SPWM cannot use the last 13% of the available line voltage. Third-harmonic injection adds the same $\tfrac16\sin3\theta$ term to all three references. It is common-mode, so it cancels in the line-to-line voltages of a three-wire system, and it flattens the reference peak to $\sqrt3/2$ of the fundamental. Space-vector PWM (SVPWM) reaches the same limit by another route:

The table gives the minimum DC link, with and without a 10% high-grid margin.

For 415 V, SPWM needs $415/0.612 = 677.7\,\mathrm{V}$ and SVPWM needs $415\times\sqrt2 = 586.9\,\mathrm{V}$, a saving of 13.4%. Sanity check: with SVPWM the line-to-line peak reaches the full DC link, the limit for any modulation. This is why three-phase string inverters use DC links of several hundred volts. Injection relies on the neutral not being used; a four-wire inverter needs care, because the common-mode term can then drive current.

Harmonics, Fourier series and THD

Any periodic voltage is a sum of sinusoids at multiples of the fundamental frequency. The symbols are:

• $h$, $n$: harmonic order, an integer ($h = 1$ is the fundamental)
• $a_n$, $b_n$: Fourier coefficients of the cosine and sine terms (V)
• $V_h = \sqrt{a_h^2 + b_h^2}$: amplitude of harmonic $h$ (V); $V_1$: the fundamental

Total harmonic distortion compares everything above the fundamental with the fundamental (peak or rms amplitudes give the same ratio):

Worked example: the square wave

Take a square wave of amplitude $V$, positive for the first half period and negative for the second. It is odd-symmetric, so every $a_n = 0$, and the two half periods contribute equally to $b_n$:

Even harmonics vanish, and harmonic $h$ is $1/h$ of the fundamental. For a $\pm400\,\mathrm{V}$ swing the fundamental peak is 509.3 V, the third 169.8 V and the fifth 101.9 V. Then:

This uses $\sum_{h\ \mathrm{odd}}1/h^2 = \pi^2/8$.

A square wave plus a filter is not enough: the lowest harmonic is at 150 Hz, only three times the fundamental, and a filter that cut it hard would also distort 50 Hz. SPWM moves the energy to frequencies hundreds of times higher, where a small filter removes it. Grid codes such as IEEE 1547 and the CEA connectivity regulations limit the current distortion an inverter may inject, so check the current edition.

The output filter: LC and LCL

With harmonics near 16 or 32 kHz, a low-pass filter can pass 50 Hz and block them. Let $L$ be the series inductance (H), $C$ the shunt capacitance (F) and $f_c$ the cutoff (Hz). For an unloaded LC divider:

The denominator vanishes at resonance, which defines the cutoff:

Well above $f_c$, the magnitude falls with the square of the frequency ratio, which is 40 dB per decade:

Worked example. Choose $L = 2\,\mathrm{mH}$ and $C = 4.7\,\mu\mathrm{F}$:

This is 33 times the grid frequency, so 50 Hz passes almost untouched, and 9.7 times below $f_s = 16\,\mathrm{kHz}$. At the switching frequency:

At 32 kHz (the unipolar cluster) it is 51.6 dB. The shortcut $-40\log_{10}(16000/1641.6)$ gives 39.6 dB, within 0.1 dB. The capacitor draws 0.34 A at 50 Hz, about 78 var or 1.6% of 5 kVA.

On a real grid: L, then LCL

A grid-connected inverter drives a stiff source whose impedance is small at high frequency, so the series inductor does most of the work. In unipolar switching at an effective $2f_s$, the current ripple peaks when the instantaneous voltage is $V_{dc}/2$:

That is 5.1% of the 30.7 A peak current of a 5 kW unit. An LCL filter adds a second inductor and gives 60 dB per decade above its resonance, so smaller inductors reach the same attenuation:

Here $L_1$ is the inverter-side inductor, $L_2$ the grid-side one and $C_f$ the capacitor. Undamped, that resonance can destabilise the current controller, so designers place it between about ten times the grid frequency and half the switching frequency, and damp it with a resistor or in firmware. Fast edges also drive leakage current through the PV-to-earth capacitance, one reason earthing matters; see earthing and surge protection for solar plants.

Grid synchronisation and power flow

To export power, the inverter must match the grid's frequency and phase. A phase-locked loop (PLL) estimates the grid phase. Let $\theta$ be the true phase, $\hat\theta$ the estimate and $v_g = \hat V\sin\theta$. Multiply the measurement by $\cos\hat\theta$:

A low-pass filter removes the second term, which sits near 100 Hz. The first is proportional to the phase error for small angles:

A PI controller turns $\varepsilon$ into a frequency correction, and an integrator turns frequency into phase:

At zero error the estimate has locked onto the grid's phase and frequency.

Real and reactive power through a reactance

Model the inverter as a voltage phasor $V_1\angle\delta$ (rms) joined to the grid $V_2\angle0^\circ$ through a series reactance $X = \omega L$ (ohms). The current is:

The complex power from the inverter is $\mathbf S = \mathbf V_1\mathbf I^*$, with $^*$ the complex conjugate:

The real part is real power $P$ and the imaginary part reactive power $Q$:

For a purely reactive link these are exact; texts write $Q \approx$ when lines also have resistance. For small $\delta$ (radians), $P \approx V_1V_2\delta/X$ and $Q \approx V_1(V_1 - V_2)/X$: the angle sets real power, and the voltage magnitude sets reactive power.

Worked example. A 5 kW inverter feeds a 230 V grid through $L = 2\,\mathrm{mH}$, so $X = 2\pi\times50\times0.002 = 0.628\,\Omega$. Unity power factor at the grid requires $V_1\cos\delta = V_2$, so $P = V_2^2\tan\delta/X$:

Then $V_1 = 230/\cos3.40^\circ = 230.4\,\mathrm{V}$ at 21.7 A. The reactive power is $Q = I^2X = 21.74^2\times0.628 = 297\,\mathrm{var}$, matching the $Q$ formula; the inductor consumes it. The table uses $V_1 = V_2 = 230\,\mathrm{V}$ on the same link.

A few degrees move kilowatts, and the maximum at 90 degrees is 84.2 kW for this link. In practice the inverter regulates its output current, with the PLL supplying the reference phase. An outer loop holds the DC-link voltage steady: if the link rises, more power is coming in than going out, so the current amplitude rises. The tracker sets what the array delivers, and the grid side exports exactly that.

S, P, Q and power factor

Apparent power $S$ (VA) is rms voltage times rms current. Real power $P$ (W) does work, and reactive power $Q$ (var) shuttles back and forth. With $\varphi$ the angle between voltage and current:

The power factor is $\mathrm{PF} = P/S = \cos\varphi$ for sinusoids. A 5 kVA inverter at PF 0.9 delivers 4.5 kW and 2.18 kvar. Because the inverter is limited in VA, reactive power reduces the real power it can export; confirm your DISCOM's settings.

Synchronisation also supports anti-islanding. If the grid fails while local load nearly matches the inverter output, the inverter could keep a local network live and endanger line workers. Inverters watch voltage, frequency and phase against set windows, and may inject a small disturbance so an island drifts out of limits and trips; IEEE 1547 and the CEA connectivity regulations cover this. The effect you notice is in what a solar inverter is: a plant stops in an outage unless it is backup-capable.

Sizing the DC-link capacitor

Return to the 100 Hz pulsation. Assume the DC side supplies constant power $P$, which is what MPPT aims for, while the AC side takes $p(t) = P(1-\cos2\omega t)$. The symbols are:

• $p_C$: power into the capacitor (W); $E$: energy stored (J)
• $C$: DC-link capacitance (F); $V_{dc}$: mean DC-link voltage (V)
• $\Delta V_{pp}$: peak-to-peak ripple voltage (V)

The capacitor absorbs the difference:

Integrating gives an energy that oscillates about its mean:

A capacitor stores $\tfrac12CV^2$, so the same swing is:

This is exact when $V_{dc}$ is the midpoint of the swing. Equating the two energies gives the sizing rule:

Worked example. A 5 kW inverter at $V_{dc} = 400\,\mathrm{V}$ with 5% peak-to-peak ripple has $\Delta V_{pp} = 20\,\mathrm{V}$:

The energy swing is 15.9 J and the voltage runs from 390 V to 410 V. Check: $\tfrac12\times1.99\,\mathrm{mF}\times(410^2 - 390^2) = 15.9\,\mathrm{J}$. The 100 Hz capacitor current has amplitude $P/V_{dc}$, so its rms value is:

Ripple-current rating matters as much as capacitance, and electrolytic capacitors, the usual choice, are a typical wear item.

The capacitor sits on the high-voltage DC link after the boost stage, not across the panels, because 100 Hz ripple across the array would make the operating point wobble and cost energy, as MPPT theory shows. A three-phase inverter has no 100 Hz term, so its capacitor only handles switching ripple.

Losses, efficiency and the switching-frequency trade-off

Conduction loss depends on current: for a MOSFET it is $R_{\mathrm{on}}I_{\mathrm{rms}}^2$, and for an IGBT $V_{CE0}I_{\mathrm{avg}} + r_{CE}I_{\mathrm{rms}}^2$. Switching loss occurs at each transition, when voltage and current overlap, and is proportional to switching frequency. Using $\bar E_{sw}$ for the average energy per switching event:

These assume two devices conduct at any instant and four switch each period; inductor, gate-drive and boost-stage losses are extra.

Worked example. Assume $R_{\mathrm{on}} = 50\,\mathrm{m}\Omega$ and a datasheet $E_{on}+E_{off} = 0.4\,\mathrm{mJ}$ at 400 V and 30 A, scaled linearly with current. With $I_{\mathrm{rms}} = 21.74\,\mathrm{A}$, $P_{\mathrm{cond}} = 2\times0.05\times21.74^2 = 47.3\,\mathrm{W}$. The cycle-average current magnitude is $2/\pi$ of the 30.74 A peak, so $\bar E_{sw} = 0.4\,\mathrm{mJ}\times(30.74/30)\times(2/\pi) = 0.261\,\mathrm{mJ}$, and at 16 kHz $P_{sw} = 4\times16000\times0.261\times10^{-3} = 16.7\,\mathrm{W}$.

The trade-off is plain. Doubling $f_s$ doubles switching loss but halves the ripple for a given inductor, or lets you halve the inductor. Higher frequency gives a smaller, cheaper filter but more heat. When you compare datasheets, such as those in top solar inverter brands in India, look at weighted efficiency across load levels and at THD at rated power, not only the peak efficiency.

If you want this analysis for your own site, covering the DC-to-AC ratio, string voltage against the inverter window and power quality, Ray2Volt can work through it with you. Start with a free power audit or see our commercial and industrial solar service.

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